Title :
DDL-based calibration techniques for timing errors in current-steering DACs
Author :
Tang, Yongjian ; Hegt, Hans ; Van Roermund, Arthur
Author_Institution :
Mixed-Signal Microelectron. Group, Eindhoven Univ. of Technol.
Abstract :
Timing errors become more and more important to dynamic performance in high-speed and high-resolution DACs. To relax the requirements on circuit design and layout complexity, two digital-delay-line (DDL) based calibration techniques for timing errors are demonstrated in this work. Matlab behavior level simulation results show that these two on-chip calibration techniques can improve the SFDR performance. The simulation results of a phase detector, the key circuit in these two calibration techniques, are given. This circuit is implemented in a CMOS 0.18mum process
Keywords :
CMOS integrated circuits; circuit complexity; circuit layout; delay lines; digital-analogue conversion; 0.18 micron; CMOS process; DDL-based calibration; circuit design; current-steering DAC; digital-delay-line; digital-to-analog converters; high-resolution DAC; high-speed DAC; layout complexity; timing errors; CMOS technology; Calibration; Circuit simulation; Clocks; Delay estimation; Detectors; Performance analysis; Phase detection; Switches; Timing;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1692532
