A new architecture for time-multiplexed FPGA and its circuit partitioning algorithm

Time-Multiplexed FPGA (TMFPGA) dramatically improves logic utilization by using time-sharing logic. In order to use TMFPGA the precedence constraints must be followed. It is a problem with high complexity to partition a circuit for implementation on a TMFPGA. In this paper, we present a new TMFPGA architecture. The precedence constraints are simplified. This is achieved by applying the same clock signal to both the flip-flop and micro register inside control logic block (CLB). They are directly accessible from outside CLB by adding two multiplexers. For execution efficiency, a control signal is added to select the desired reconfiguration memory plane. We also propose a novel two phase circuit partitioning algorithm for this new architecture to minimize the number of stages and balance the area of each stage. Experimental results for the benchmark circuits demonstrate the effectiveness of our partitioning algorithm.