An efficient novel latch design for sequential applications

Due to increased demand of portable and battery operated devices, ultra-low power and high speed devices with less area requirement are vital nowadays. Latch is the basic element for all the sequential circuits. This research paper proposes a 5-transistor level sensitive flip-flop and comparison results with the existing design are presented. Proposed and existing designs are paralleled in 32nm and 22nm technologies to check their technology independence. Comparative simulations demonstrate that the proposed latch offers better results in terms of power, area and speed.