Title :
Chaos in delay locked loop
Author :
Wang, Ping-Ying ; Chou, C.-H. ; Kao, Hsueh-Wu
Author_Institution :
Analog Circuit Design Div., MediaTek Inc., Hsinchu
Abstract :
We prove existence of chaos in delay locked loops (DLL). It is the first time that the chaotic phenomenon in DLLs is reported. The DLL is designed to verify predictions of theory analysis. The prediction of the theory is confirmed by circuit simulation. The chip size is only 0.015mm 2, thus provides a low cost analog solution to randomize clock phases and simple circuits to study chaos
Keywords :
chaos; clocks; delay lock loops; network analysis; chaotic phenomenon; circuit simulation; delay locked loop; randomized clock phase; Capacitors; Chaos; Charge pumps; Circuits; Clocks; Delay effects; Detectors; Propagation delay; Size control; Voltage control;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1692564
