VLSI architecture for 4 /spl times/ 4 16-QAM V-BLAST decoder

Author

Sobhanmanesh, Fariborz ; Nooshabadi, Saeid

Author_Institution

Sch. of Electr. Eng. & Telecommun., New South Wales Univ., Sydney, NSW

fYear

2006

fDate

21-24 May 2006

Abstract

This paper presents the VLSI architecture for the V-BLAST detection for a 4 times 4 16-QAM MIMO wireless communication systems based on the QR factorization technique. We present the design and optimization of the pre decoder block based on the CORDIC rotator processors. We also present the architecture of the back substitution symbol interference cancellation (SIC) block that eliminates the need for division and multiplication, thereby substantially, reducing the hardware cost, without compromising the numerical stability. The proposed VLSI architecture is implemented on an Altera Stratix FPGA. A detection throughput of 149 Mb/s is achieved on this platform. This paper also investigates the use of a parallel decoding scheme to improve the BER performance

Keywords

VLSI; decoding; digital arithmetic; error statistics; field programmable gate arrays; interference suppression; logic design; microprocessor chips; quadrature amplitude modulation; radiocommunication; 149 Mbit/s; 16-QAM decoder; Altera Stratix FPGA; BER performance; CORDIC rotator processors; MIMO wireless communication; QR factorization; V-BLAST decoder; VLSI architecture; parallel decoding scheme; symbol interference cancellation; Costs; Decoding; Design optimization; Hardware; Interference cancellation; MIMO; Numerical stability; Silicon carbide; Very large scale integration; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1692580

Filename

1692580