DocumentCode
2530321
Title
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing
Author
Moiseev, Konstantin ; Wimer, Shmuel ; Kolodny, Avinoam
Author_Institution
Dept. of Electr. Eng., Technion, Haifa
fYear
2006
fDate
21-24 May 2006
Abstract
This paper addresses the problem of ordering and sizing parallel wires in a single metal layer within an interconnect channel of a given width, such that cross-capacitances are optimally shared for circuit timing optimization. Using an Elmore delay model including cross capacitances for a bundle of wires, we show that an optimal wire ordering is uniquely determined, such that best timing can be obtained by proper allocation of wire widths and inter-wire spaces. The optimal order, called BMI (balanced monotonic interleaved) depends only on the size of drivers for a wide range of cases. Heuristics are presented for simultaneous ordering, sizing and spacing of wires. Examples for 90-nanometer technology are analyzed and discussed
Keywords
delays; integrated circuit interconnections; integrated circuit layout; nanotechnology; timing; 90 nm; Elmore delay model; balanced monotonic interleaved; cross capacitances; heuristic technique; optimal wire ordering; parallel wires; timing optimization; wire sizing; wire spacing; Capacitance; Delay; Driver circuits; Integrated circuit interconnections; Noise reduction; Sorting; Space technology; Throughput; Timing; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location
Island of Kos
Print_ISBN
0-7803-9389-9
Type
conf
DOI
10.1109/ISCAS.2006.1692589
Filename
1692589
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