A pipelined VLSI architecture for a list sphere decoder

Since finding the nearest point in a lattice for multi-input multi-output (MIMO) channels is NP-hard, simplified algorithms such as a sphere decoder (SD) have been proposed. With simple modification of SD, a list sphere decoder (LSD), soft information can be extracted for channel decoding and iterative detection/decoding. However, generating such information increases the computational complexity for selecting a specific number of candidate lattice points. In this paper an efficient pipelined VLSI architecture for LSD is presented and its complexity is analyzed. The architecture is constructed with three pipeline stages, two stages for metric calculation units (MCU) and one stage for metric enumeration unit (MEU). It also has three storage units and list units for three successive input MIMO vectors. The pipeline can increase the operating clock frequency and keep one-node-per-cycle policy, so that the average throughput can enhance according to the increment of the clock frequency