• DocumentCode
    253102
  • Title

    Performance enhancementof SOI power LDMOSFET using trench gate technology

  • Author

    Punetha, Mayank ; Singh, Yogang

  • Author_Institution
    Dept. of Electron. & Commun. Eng., G.B. Pant Eng. Coll., Pauri Garhwal, India
  • fYear
    2014
  • fDate
    9-11 May 2014
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    In this paper, we propose that the performance of a conventional power metal-oxide-semiconductor field effect transistor (LDMOSFET) on SOI can be improved by placing a gate in the trench built in the drift region to enhance the current conduction and reduced-surface electric field (RESURF)effect. The RESURF effect can be further improved by using an additional trench in the drift region filled with oxide. Using 2-dimensional numerical simulations, the performance of the proposed device is evaluated and compared with the conventional power MOSFET on SOI. The simulation results show that abetter trade-off between breakdown voltage and ON-resistance can be obtained using proposed structure. The figure-of-merit(FOM) of the proposed device is 3 times better than the conventional power LDMOSFET on SOI for the same cell pitch.
  • Keywords
    isolation technology; power MOSFET; silicon-on-insulator; RESURF effect; SOI power LDMOSFET; current conduction; laterally diffused power MOSFET; metal oxide semiconductor field effect transistor; performance enhancement; reduced surface electric field effect; trench gate technology; Lead; Logic gates; Performance evaluation; Silicon; Substrates; Telecommunications; LDMOSFET; SOI; breakdown voltage; figure of merit; lateral; specific ON-resistance; trench-gate;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Recent Advances and Innovations in Engineering (ICRAIE), 2014
  • Conference_Location
    Jaipur
  • Print_ISBN
    978-1-4799-4041-7
  • Type

    conf

  • DOI
    10.1109/ICRAIE.2014.6909181
  • Filename
    6909181