Title :
Power supply variation effects on timing characteristics of clocked registers
Author :
Roberts, William R. ; Velenis, Dimitrios
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL
Abstract :
Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of variations in the power supply voltage (VDD) on the timing characteristics of registers are investigated in this paper. The sensitivity of the setup time and data propagation delay to power supply variations is demonstrated for four different register designs. Design modifications are proposed in order to enhance the robustness of each register design under VDD variations
Keywords :
clocks; delays; flip-flops; integrated circuit design; logic design; synchronisation; clocked registers; power supply variations; propagation delay; register design; sensitivity; synchronous system; timing constraints; Circuits; Clocks; Frequency; Power supplies; Propagation delay; Registers; Robustness; Timing; Uncertainty; Voltage;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1692630
