Title :
A new flash-erase EEPROM cell with a sidewall select-gate on its source side
Author :
Naruke, K. ; Yamada, S. ; Obi, E. ; Taguchi, S. ; Wada, M.
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
A novel flash-erase EEPROM (electrically erasable PROM) cell is described. It consists of a stacked-gate MOSFET with a sidewall select gate on the source side of the FET (SISOS cell). Three layers of polysilicon are used. The cell has a self-aligned structure which makes it possible to realize a small cell area of 4.0*3.5 mu m/sup 2/ with 1.0- mu m technology. It also has a select gate which prevents undesirable leakage current due to overerasing. The cell is programmed by channel hot electron injection at the source side and erased by Fowler-Nordheim tunneling of electrons from the floating gate to the drain. The programming by source-side injection makes it possible for the drain junction to be optimized independently of hot electron generation and for the erasure to be achieved with no degradation in programmability.<>
Keywords :
EPROM; MOS integrated circuits; PLD programming; hot carriers; integrated memory circuits; tunnelling; 1 micron; Fowler-Nordheim tunneling; SISOS cell; channel hot electron injection; electrically erasable PROM; flash-erase EEPROM cell; floating gate; programming; self-aligned structure; sidewall select-gate; source-side injection; stacked-gate MOSFET; three layer polysilicon structure; Degradation; EPROM; Electrons; Etching; FETs; Implants; Leakage current; Nonvolatile memory; Tunneling; Voltage;
Conference_Titel :
Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1989.74353
