Title :
An analytical propagation delay model with power supply noise effects
Author :
Pude, Mark ; Washburn, Clyde ; Mukund, P.R. ; Abe, Kouichi ; Nishi, Yoshinori
Author_Institution :
Dept. of Electr. Eng., Rochester Inst. of Technol., NY
Abstract :
This paper presents an analytical model for CMOS logic propagation delay which includes the effect of power supply noise. Using the nth power law model of MOSFETs, two scenarios are addressed: self-induced power supply noise and globally-induced power supply noise. The analytical model is verified in simulation for both cases. The self-induced noise model matches simulation to within 0.36%. The globally-induced noise model matches simulation to within 5% for typical input rise time values and never more than 15% under extreme conditions
Keywords :
CMOS logic circuits; integrated circuit modelling; integrated circuit noise; power supply circuits; CMOS logic propagation delay model; MOSFET; globally-induced power supply noise; power law model; power supply noise effects; self-induced power supply noise; Analytical models; CMOS logic circuits; Circuit noise; Circuit simulation; Crosstalk; MOSFETs; Power supplies; Propagation delay; Semiconductor device modeling; Voltage;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1692664
