• DocumentCode
    2531902
  • Title

    Defect characterization and yield analysis of array-based nanoarchitecture

  • Author

    Zhang, Shanrui ; Choi, Minsu ; Park, Nohpill

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Missouri Univ., Rolla, MO, USA
  • fYear
    2004
  • fDate
    16-19 Aug. 2004
  • Firstpage
    50
  • Lastpage
    52
  • Abstract
    With molecular-scale materials and fabrication techniques recently developed, high-density computing systems in nanometer domain emerge. An array-based nanoarchitecture has been recently proposed based on nanowires such as carbon nanotubes (CNTs), silicon nanowires (SiNWs). High-density nanoarray-based systems consisting of nanometer-scale elements are likely to have many imperfections; thus, defect-tolerance is considered as one of the most significant challenges. In this paper, we propose a probabilistic yield model for the array-based nanoarchitecture. The proposed yield model can be used 1) to accurately estimate the raw and net array densities, and 2) to design and optimize more defect and fault-tolerant systems based on the array-based nanoarchitecture.
  • Keywords
    carbon nanotubes; elemental semiconductors; failure analysis; fault tolerance; nanoelectronics; nanotube devices; nanowires; probability; silicon; C; Si; array-based nanoarchitecture; carbon nanotubes; defect-tolerance; fault-tolerant systems; high-density computing systems; imperfections; molecular-scale materials; nanometer domain; net array densities; probabilistic yield model; raw array densities; silicon nanowires; yield analysis; Chemical elements; Decoding; Design optimization; Fault tolerant systems; Lithography; Logic arrays; Nanowires; Silicon; Wires; Yield estimation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Nanotechnology, 2004. 4th IEEE Conference on
  • Print_ISBN
    0-7803-8536-5
  • Type

    conf

  • DOI
    10.1109/NANO.2004.1392246
  • Filename
    1392246