Design of low power and energy efficient 5 × 5 multipliers

In this paper we present two, low power and high speed array multiplier cells, designed with an alternate logic structure of full adder that achieves more efficiency in terms of Energy Delay Product (EDP). All the multipliers were designed using 0.18μm technology and comparison was carried out for the performance against other multipliers in terms of power delay product (PDP) and Energy delay product. Different reported adder designs were used to implement the array multipliers. The proposed multiplier-1 and proposed multiplier-2 were compared with the one with lowest EDP and a reduction of 62% and 58% respectively is achieved.