Power system on a chip (PSoC)

This paper addresses modeling issues behind the development of a hardware analog emulator of power system behavior referred to as a power system on a chip (PSoC). The paper reviews various problems and proposed solutions encountered from the design stage to PC-board hardware implementation to anticipated VLSI implementation. It has already been noted that using analog emulation for power system analysis allows for reduction in computation time, without significant loss in accuracy, compared to numerical methods. This is further validated in this paper through observations obtained from comparative runs between software and analog hardware environments