Ultimate CMOS density limits: measured source drain resistance in ultra small devices

The dependence of the extrinsic component of the series resistance of CMOS devices on the size of the source/drain areas has been explored experimentally. Trench isolated depletion mode n- and p-channel MOSFETs with silicided source/drain areas from 1.7*2 mu m/sup 2/ to 0.2*0.3 mu m/sup 2/ have been fabricated using electron beam lithography. A sheet resistance of 3-5 Omega / Square Operator and a contact resistivity of p/sub c/=3-6*10/sup -7/ Omega -cm/sup -2/ have been obtained for the TiSi/sub 2/ contact technology. The measured extrinsic series resistance is observed to increase rapidly for source/drain sizes below the contact transfer length of 0.6-0.8 mu m and to become larger than the intrinsic series resistance component. Based on these data, the upper limit for the CMOS current drive capability and the lower limit for propagation delay as a function of source/drain size are established.<>