Implementation of area and energy efficient full adder cell

Author

Tiwari, Niyati ; Sharma, Ritu ; Parihar, Rajesh

Author_Institution

Medi Caps Group of Instn., Electron. & Commun., Indore, India

fYear

2014

fDate

9-11 May 2014

Firstpage

1

Lastpage

5

Abstract

This paper presents a low power full adder cell designed with transmission gate and pass-transistor logic styles that lead to have a reduced area, power and delay. We compared 28T conventional CMOS full-adders to 14T and 16T full adder cell, in terms of speed, power consumption and area. All the full-adders were designed with a 0.25um CMOS technology, and were tested using a tannerv13.0. After simulating CMOS and pass transistors based full adder, compared the average power consumption. 16T based Full adder consumed 98% less power compared to 28T conventional CMOS full adder.

Keywords

CMOS logic circuits; adders; energy conservation; logic arrays; logic design; logic gates; logic testing; power consumption; transistor circuits; CMOS full-adders; area efficient full adder cell; energy efficient full adder cell; full adder design; full adder test; low power full adder cell; pass-transistor logic styles; power consumption; size 0.25 mum; tannerv13.0; transmission gate; Adders; CMOS integrated circuits; CMOS technology; Multiplexing; Complementary Metal Oxide Semiconductor (CMOS); Full Adder (FA); Pass transistor logic (PTL); Transmission Gate (TG);

fLanguage

English

Publisher

ieee

Conference_Titel

Recent Advances and Innovations in Engineering (ICRAIE), 2014

Conference_Location

Jaipur

Print_ISBN

978-1-4799-4041-7

Type

conf

DOI

10.1109/ICRAIE.2014.6909248

Filename

6909248