An integrated system for statistical testing of pseudo-random generators in FPGA devices

This paper presents results of studies on development of the system for testing of pseudo-random binary sequences produced by chaotic generators implemented in programmable devices. This task requires a large amount of computing resources due to the complex form of statistical tests. The proposed solution is a flexible, platform-independent integrated test-bed and can be extended by new modules. It has been proved, that the described system significantly simplifies testing of pseudorandom generators implemented in FPGA devices.