Behavioral synthesis with SystemC and PSL assertions for interface specification

Behavioral synthesis of digital circuits offers an effective way to deal with the increasing complexity of hardware design. Even though it has been the subject of considerable research efforts over the last thirty years, practical implementations have not been widely accepted by industry yet. This happens due to the fact that designers demand interaction with the design process, which allows them to submit different constraints, especially with respect to interface specifications and specific I/O protocols. This paper presents an interactive synthesis environment that accepts untimed behavioral descriptions in SystemC and PSL assertions. From the latter, it extracts interface compliance requirements and uses them to perform timing constrained high-level synthesis from the former. Overall, the presented approach raises the feasibility for high-level design space exploration, by supporting better user control of automated synthesis results, and takes full advantage of modern assertion based verification methodologies