2-Bit magnitude comparator using GDI technique

Author

Shekhawat, Vijaya ; Sharma, Toshi ; Sharma, K.G.

Author_Institution

FET, ECE Dept., MITS, Sikar, India

fYear

2014

fDate

9-11 May 2014

Firstpage

1

Lastpage

5

Abstract

In recent years, low power design has become one of the prime focuses for the digital VLSI circuit. Keeping the same in mind a new design of 2-Bit GDI based Magnitude Comparator has been proposed and implemented with the help of full adder which is the basic building block of ALU. Proposed GDI technique based magnitude comparator has an advantage of less power consumption with respect to various design parameters; less on-chip area covered as less number of transistors are required in circuit design as compared to conventional CMOS magnitude comparator. Both the circuits are designed and simulated using Tanner EDA Tool version 12.6 at 45nm process technology.

Keywords

comparators (circuits); field effect logic circuits; integrated circuit design; ALU basic building block; GDI technique; Tanner EDA Tool version 12.6; circuit design; digital VLSI circuit; gate diffusion input technique; magnitude comparator; size 45 nm; CMOS integrated circuits; CMOS technology; Inverters; Logic gates; MOS devices; Marine animals; Nanoscale devices; Full Adder and Low Power; GDI Technique; Magnitude Comparator;

fLanguage

English

Publisher

ieee

Conference_Titel

Recent Advances and Innovations in Engineering (ICRAIE), 2014

Conference_Location

Jaipur

Print_ISBN

978-1-4799-4041-7

Type

conf

DOI

10.1109/ICRAIE.2014.6909270

Filename

6909270