Title :
FPGA implementation of FIR filter using M-bit parallel distributed arithmetic
Author :
Jeng, Shiann-Shiun ; Lin, Hsing-Chen ; Chang, Shu-Ming
Author_Institution :
Dept. of Electr. Eng., National Dong Hwa Univ., Hualien
Abstract :
An efficient architecture for a FPGA symmetry FIR filter is proposed that employs M-bit parallel-distributed arithmetic (M-bit PDA). The partial product is pre-calculated and saved into the distributed RAM. This eliminates the large amount of logic needed to compute multiplication results. The proposed architecture consumes less area and offers higher speed operation because the multiplier is omitted. Altera APEX20KE is used as a target device. Thus, the proposed architecture has high processing speed and small area
Keywords :
FIR filters; distributed arithmetic; field programmable gate arrays; parallel architectures; random-access storage; Altera APEX20KE; FIR filter; FPGA; M-bit PDA; M-bit parallel distributed arithmetic; RAM; multiplier; Arithmetic; Electrical products industry; Electronic mail; Field programmable gate arrays; Finite impulse response filter; Input variables; Logic; Personal digital assistants; Shift registers; Table lookup;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1692725
