The CORDIC-inside-lifting architecture for constant-coefficient hardware quaternion multipliers

This paper presents an architecture for constant-coefficient hardware quaternion multipliers, which is based on combining the CORDIC algorithm with a lifting scheme. Real multipliers related to lifting steps are approximated using 2D CORDIC iterations, or bit shifts and additions. The resulting multiplierless scheme requires less chip area than a direct fixed-point implementation of the multiplications and is better suited to pipelining. However its design and implementation are difficult, which has been verified by VHDL/FPGA-based development of a universal processing unit for multiplying quaternions which is also described herein. Although the precision of CORDIC-based computations is finite, the lifting scheme ensures that obtainable approximations of hypercomplex multiplications are perfectly invertible. Because of this property, the solution can find applications in lossless compression of audio and video data.