DocumentCode :
2532933
Title :
A Translation Framework for Virtual Execution Environment on CPU/GPU Architecture
Author :
Dong, Guoxing ; Chen, Kai ; Zhu, Erzhou ; Zhang, Yichao ; Qi, Zhengwei ; Guan, Haibing
Author_Institution :
Sch. of Software, Shanghai Jiaotong Univ., Shanghai, China
fYear :
2010
fDate :
18-20 Dec. 2010
Firstpage :
130
Lastpage :
137
Abstract :
GPUs are many-core processors with tremendous computational power. However, as automatic parallelization has not been realized yet, developing high-performance parallel code for GPUs is still very challenging. The paper presents a novel translation framework designed for virtual execution environment based on CPU/GPU architecture. It addresses two major challenges of taking advantage of general purpose computation on graphics processing units (GPGPU) to improve performance: no rewriting the existing source code and resolving binary compatibility issues between different GPUs. The translation framework uses semi-automatic parallelization technology to port existing code to explicitly parallel programming models. It not only offers a mapping strategy from X86 platform to CUDA programming model, but also synchronizes the execution between the CPU and the GPUs. The input to our translation framework is parallelizable part of the program within binary code. With an additional information related to the parallelizable part, the translation framework transforms the sequential code into PTX code and execute it on GPUs. Experimental results on several programs from CUDA SDK Code Samples and Parboil Benchmark Suite show that our translation framework could achieve very high performance, even up to several tens of times speedup over the X86 native version.
Keywords :
computer graphic equipment; coprocessors; multiprocessing systems; parallel architectures; CPU-GPU Architecture; CUDA SDK code samples; CUDA programming model; Parboil benchmark suite; X86 platform; many core processors; virtual execution environment; Computer architecture; Driver circuits; Graphics processing unit; Instruction sets; Kernel; Programming; Registers; CUDA; GPGPU; Parallelization; Translator;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Architectures, Algorithms and Programming (PAAP), 2010 Third International Symposium on
Conference_Location :
Dalian
Print_ISBN :
978-1-4244-9482-8
Type :
conf
DOI :
10.1109/PAAP.2010.53
Filename :
5715074
Link To Document :
بازگشت