DocumentCode
2533003
Title
Dual-VT SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 μm technology generation
Author
Hamzaoglu, Fatih ; Ye, Yibin ; Keshavarzi, Ali ; Zhang, Kevin ; Narendra, Siva ; Borkar, Shekhar ; Stan, Mircea ; De, Vivek
Author_Institution
Microprocessor Res. Labs., Intel Corp., Hillsboro, OR, USA
fYear
2000
fDate
2000
Firstpage
15
Lastpage
19
Abstract
Comparisons among different dual-VT design choices for a large on-chip cache with single-ended sensing show that the design using a dual-VT cell and low-VT peripheral circuits is the best, and provides 10% performance gain with 1.2x larger active leakage power, and 1.6% larger cell area compared to the best design using high-VT cells.
Keywords
SRAM chips; cache storage; computer power supplies; delays; electrical faults; integrated circuit design; semiconductor device noise; 0.13 μm technology; 0.13 mum; 10% performance gain; dual-VT SRAM; full-swing single-ended bit line sensing; high-VT cells; high-performance on-chip cache; leakage; low-VT peripheral circuits; noise; single-ended sensing; Bismuth; Degradation; Delay effects; Delay lines; Inverters; Leakage current; MOS devices; Random access memory; Stability; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on
Print_ISBN
1-58113-190-9
Type
conf
DOI
10.1109/LPE.2000.155246
Filename
876750
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