Statistical design of a multiplier using a low voltage square-law CMOS cell

Author

Tarim, Tuna B. ; Kuntman, H. Hakan ; Ismail, Mohammed

Author_Institution

Dept. of Electron. Eng., Istanbul Tech. Univ., Turkey

fYear

1998

fDate

24-27 Nov 1998

Firstpage

25

Lastpage

28

Abstract

The statistical design of a new multiplier using the square-law characteristics of MOS transistors in the saturation region is discussed in this paper. The multiplier is statistically robust and has a good yield. Initial simulation results of the circuit have been given and the offset current and nonlinearity of the multiplier has been statistically examined. Response Surface Methodology and Design of Experiment techniques were used as statistical VLSI design tools combined with the statistical MOS model. Device size optimization and yield enhancement have been demonstrated

Keywords

CMOS analogue integrated circuits; VLSI; analogue multipliers; design of experiments; integrated circuit design; statistical analysis; surface fitting; LV square-law CMOS cell; MOS transistors; design of experiment techniques; device size optimization; low voltage CMOS cell; nonlinearity; offset current; response surface methodology; saturation region; square-law characteristics; statistical MOS model; statistical VLSI design tools; statistical design; yield enhancement; Circuit simulation; Frequency response; Low voltage; MOSFETs; Power supplies; Process design; Semiconductor device modeling; Threshold voltage; Transconductance; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on

Conference_Location

Chiangmai

Print_ISBN

0-7803-5146-0

Type

conf

DOI

10.1109/APCCAS.1998.743649

Filename

743649