DocumentCode
2533158
Title
Pipeline processing in real-time of CABAC decoder based on FPGA
Author
Petrovsky, Alexey ; Stankevich, Andrew ; Petrovskyi, A.
Author_Institution
Comput. Eng. Dept., Belarusian State Univ. of Inf. & Radioelectron., Minsk, Belarus
fYear
2012
fDate
18-21 Sept. 2012
Firstpage
1
Lastpage
4
Abstract
This paper presents the implementation on the FPGA module CABAC decoder for h.264. The organization of the computational process is based on the pipe-line architecture that allows to simultaneously decoding multiple bins. This scheme is implemented on FPGA with clock frequency equal 96MHz and provides decoding of one bin per cycle.
Keywords
adaptive codes; arithmetic codes; binary codes; data compression; decoding; field programmable gate arrays; pipeline processing; video coding; CABAC decoder; FPGA module; H.264; clock frequency; context-adaptive binary arithmetic coding; frequency 96 MHz; multiple bind decoding; pipeline architecture; pipeline processing; Context; Context modeling; Decoding; Field programmable gate arrays; Program processors; Syntactics; Video coding;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals and Electronic Systems (ICSES), 2012 International Conference on
Conference_Location
Wroclaw
Print_ISBN
978-1-4673-1710-8
Electronic_ISBN
978-1-4673-1709-2
Type
conf
DOI
10.1109/ICSES.2012.6382256
Filename
6382256
Link To Document