DocumentCode :
2533465
Title :
Cache miss heuristics and preloading techniques for general-purpose programs
Author :
Ozawa, Toshihiro ; Kimura, Yasunori ; Nishizaki, Shinichiro
Author_Institution :
Fujitsu Labs. Ltd., Kawasaki, Japan
fYear :
1995
fDate :
29 Nov-1 Dec 1995
Firstpage :
243
Lastpage :
248
Abstract :
Previous research on hiding memory latencies has tended to focus on regular numerical programs. This paper presents a latency-hiding compiler technique that is applicable to general-purpose C programs. By assuming a lock-up free cache and instruction score-boarding, our technique `preloads´ the data that are likely to cause a cache-miss before they are used, and thereby hiding the cache miss latency. We have developed simple compiler heuristics to identify load instructions that are likely to cause a cache-miss. Experimentation with a set of SPEC92 benchmarks shows that our heuristics are successful in identifying 85% of cache misses. We have also developed an algorithm that flexibly schedules the selected load instruction and instructions that use the loaded data to hide memory latency. Our simulation suggests that our technique is successful in hiding memory latency and improves the overall performance
Keywords :
C language; cache storage; program compilers; storage management; C programs; SPEC92 benchmarks; cache miss; compiler; compiler heuristics; general-purpose programs; instruction score-boarding; latency-hiding; load instructions; lock-up free cache; performance; preloading; Computational modeling; Computer simulation; Delay; Laboratories; Load flow analysis; Processor scheduling; Program processors; Scheduling algorithm; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microarchitecture, 1995., Proceedings of the 28th Annual International Symposium on
Conference_Location :
Ann Arbor, MI
ISSN :
1072-4451
Print_ISBN :
0-8186-7349-4
Type :
conf
DOI :
10.1109/MICRO.1995.476832
Filename :
476832
Link To Document :
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