• DocumentCode
    2533485
  • Title

    Alternative implementations of hybrid branch predictors

  • Author

    Po-Yung ; Hao, Chang Eric ; Patt, Yale N.

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
  • fYear
    1995
  • fDate
    29 Nov-1 Dec 1995
  • Firstpage
    252
  • Lastpage
    257
  • Abstract
    Very accurate branch prediction is an important requirement for achieving high performance on deeply pipelined, superscalar processors. To improve on the prediction accuracy of current single-scheme branch predictors, hybrid (multiple-scheme) branch predictors have been proposed (McFarling (1993), Chang et al. (1994)). These predictors combined multiple single-scheme predictors into a single predictor. They use a selection mechanism to decide for each branch, which single-scheme predictor to use. The performance of a hybrid predictor depends on its single-scheme predictor components and its selection mechanism. Using known single-scheme predictors and selection mechanisms, this paper identifies the most effective hybrid predictor implementation. In addition, it introduces a new selection mechanism, the 2-level selector, which further improves the performance of the hybrid branch predictor
  • Keywords
    performance evaluation; pipeline processing; branch prediction; hybrid branch predictors; hybrid predictor; performance; pipelined; prediction accuracy; superscalar processors; Accuracy; Costs; Counting circuits; History; Microprocessors; Pipelines; Prediction algorithms; Runtime;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microarchitecture, 1995., Proceedings of the 28th Annual International Symposium on
  • Conference_Location
    Ann Arbor, MI
  • ISSN
    1072-4451
  • Print_ISBN
    0-8186-7349-4
  • Type

    conf

  • DOI
    10.1109/MICRO.1995.476833
  • Filename
    476833