DocumentCode :
2533498
Title :
A low power SoC bus with low-leakage and low-swing technique
Author :
Oh, Kwang-II ; Cho, Seunghyun ; Kim, Lee-Sup
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., KAIST, Daejeon
fYear :
2006
fDate :
21-24 May 2006
Abstract :
A novel low power SoC bus with low-leakage and low swing technique is proposed. The repeater used in the bus lines effectively reduces leakage power through stacking effect, not losing its logic values even in sleep mode. The proposed SoC bus reduces not only the leakage power in the normal active/sleep mode but also both dynamic and leakage power in the low swing operation mode. The proposed scheme reduces the total power by 44.5% compared to the conventional SoC bus architecture
Keywords :
digital integrated circuits; low-power electronics; repeaters; system buses; system-on-chip; low-leakage technique; low-power SoC bus; low-swing technique; power consumption; CMOS technology; Digital circuits; Energy consumption; Inverters; Logic; MOSFET circuits; Power MOSFET; Repeaters; Stacking; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
Type :
conf
DOI :
10.1109/ISCAS.2006.1692761
Filename :
1692761
Link To Document :
بازگشت