DocumentCode :
253350
Title :
FPGA implementation of Itoh-Tsujii inversion algorithm
Author :
Kodali, Ravi Kishore ; Amanchi, Chandana N. ; Kumar, Sudhakar ; Boppana, Lakshmi
Author_Institution :
Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol., Warangal, India
fYear :
2014
fDate :
9-11 May 2014
Firstpage :
1
Lastpage :
5
Abstract :
Elliptic Curve Cryptography (ECC) has been gaining popularity due to its shorter key size requirements. It uses arithmetic operations including addition, subtraction, multiplication and inversion in finite fields. For an efficient implementation of ECC, it is very important to carry out these operations faster using lesser resources. The in version operation consumes most of the time and more resources. The Itoh-Tsujii algorithm can be used to carry out the computation of multiplicative inverse by making use of Brauer addition chains in less time. This work presents an FPGA implementation of the multiplicative inversion for the key lengths of 194-, 233-, and 384- bits. A resource comparison for these key lengths is also made. This work uses Sunar-Koc multiplier for the finite field, GF(2m) multiplication.
Keywords :
field programmable gate arrays; matrix multiplication; public key cryptography; Brauer addition chains; ECC; FPGA; GF(2m) multiplication; Itoh-Tsujii inversion algorithm; Sunar-Koc multiplier; arithmetic operation; elliptic curve cryptography; multiplicative inverse; Elliptic curve cryptography; Equations; Field programmable gate arrays; ECC; inversion; multiplication;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Recent Advances and Innovations in Engineering (ICRAIE), 2014
Conference_Location :
Jaipur
Print_ISBN :
978-1-4799-4041-7
Type :
conf
DOI :
10.1109/ICRAIE.2014.6909308
Filename :
6909308
Link To Document :
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