A 3.0V 12b 120 Msample/s CMOS pipelined ADC

A 12b pipelined ADC incorporating an improved timing scheme for high-speed operation achieves better than 60 dB SNDR for input frequencies up to Nyquist at 120 Msample/s. The proposed timing scheme improves the amplifier settling of MDACs and operating speed of comparators. The measured DNL and INL are plusmn0.60 LSB and plusmn1.48 LSB, respectively. The ADC fabricated in a 0.13 mum CMOS process occupies 1.03 mm² active die area and consumes 315 mW under a 3.0V power supply