A 3.0 V 72mW 10b 100 MSample/s Nyquist-rate CMOS pipelined ADC in 0.54 mm/sup 2/

A 3.0 V 10b 100 MSample/s Nyquist-rate CMOS pipelined ADC is presented. The ADC adopts a modified 1.5-bit/stage and multi-bit/stage pipelined architecture for low power consumption and small die area. The proposed operational amplifier with low parasitic capacitance reduces the power consumption and die area. This ADC achieves better than 56.3dB SDNR at 100 MSample/s for a 100MHz input frequency. It exhibits higher than 56.4dB SNDR up to 140 MSample/s for a 5MHz input frequency. The measured DNL and INL of the ADC are plusmn0.23 LSB and plusmn0.33 LSB, respectively. The ADC fabricated in a 0.13 mum CMOS technology occupies only 0.54 mm² die area and consumes 72mW under a 3.0V supply including on-chip voltage reference circuit