DocumentCode
2533543
Title
Low power self-timed radix-2 division
Author
Won, Jae-Hee ; Choi, Kiyoung
Author_Institution
Sch. of Electr. Eng., Seoul Nat. Univ., South Korea
fYear
2000
fDate
2000
Firstpage
210
Lastpage
212
Abstract
A self-timed radix-2 division scheme for low power consumption is proposed. By replacing dual-rail dynamic circuits in non-critical data paths with single-rail static circuits, power dissipation is decreased, yet performance is maintained by speculative remainder computation. SPICE simulation results show that the proposed design can achieve 33.8-ns latency for 56-bit mantissa division and 47% energy reduction compared to a fully dual-rail version.
Keywords
SPICE; circuit simulation; dividing circuits; logic simulation; low-power electronics; redundant number systems; 33.8 ns; SPICE simulation results; dual-rail dynamic circuits; energy reduction; latency; power consumption; power dissipation; self-timed radix-2 division scheme; single-rail static circuits; speculative remainder computation; Adders; Arithmetic; Circuits; Computational modeling; Delay; Energy consumption; Permission; Power dissipation; Power engineering computing; SPICE;
fLanguage
English
Publisher
ieee
Conference_Titel
Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on
Print_ISBN
1-58113-190-9
Type
conf
DOI
10.1109/LPE.2000.155280
Filename
876784
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