A performance-driven global routing algorithm with wire-sizing and buffer-insertion

This paper presents a timing-driven multi-layer global routing algorithm with wire-sizing and buffer-insertion. Wire-widening and buffer insertion allow us to reduce the path delay so that we can obtain a high-performance layout. In the proposed algorithm, first, a routing topology is determined with minimizing the delay of a net from the source of a net to each root of subtrees of the tree. Next the algorithm assigns nets to each layer under timing constraints and routes nets considering routability and performs wire-sizing and buffer-insertion to reduce the path delay. Then, HV-routing of nets is performed based on the routing trees obtained in the first phase, considering timing constraint. Finally, we verify the timing constraints and reroute nets based on the criticality of each net to determine which nets are suitable for wire-sizing and buffer-insertion. Experimental results show the effectiveness of our global routing method under timing constraints