DocumentCode :
2533576
Title :
A 3-D global routing technique for routability assessment
Author :
Tanprasert, Thitipong ; Lursinsap, Chidchanok
Author_Institution :
Dept. of Comput. Sci., Assumption Univ., Bangkok, Thailand
fYear :
1998
fDate :
24-27 Nov 1998
Firstpage :
129
Lastpage :
132
Abstract :
This paper concerns a problem of layout generation in the 3-D space model where modules to be interconnected and all interconnections are treated as 3-D objects. A placement of modules will not be usable if it does not allow the routing procedure to complete all the required interconnections. This paper presents a global routing technique which attempts to route along a highly routable path in a 3-D placement. Assuming the use of a minimum Steiner tree algorithm which runs in O(n 2), where n is the number of interconnected vertices, the running time of the global routing process is O(n2) for each net. Thus its efficiency supports its integration with an iterative placement technique
Keywords :
circuit layout CAD; integrated circuit layout; network routing; trees (mathematics); 3D global routing technique; 3D placement; 3D space model; interconnections; iterative placement technique; layout generation; minimum Steiner tree algorithm; module placement; routability assessment; Computer science; Cost function; Iterative algorithms; Mathematics; Phase estimation; Routing; Topology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on
Conference_Location :
Chiangmai
Print_ISBN :
0-7803-5146-0
Type :
conf
DOI :
10.1109/APCCAS.1998.743675
Filename :
743675
Link To Document :
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