Modeling and simulation of wideband low jitter frequency synthesizer

This paper presents modeling and simulation of a wideband low jitter frequency synthesizer. The proposed system uses two phase-locked loops (PLLs) connected in cascade. The first PLL uses a voltage-controlled crystal oscillator (VCXO) to eliminate the input jitter and the second one is a wideband PLL. One important advantage of using the proposed system is that it uses only one VCXO for multiple carrier frequencies, while reducing the jitter considerably. The MATLAB Simulink simulation results show that the jitter could be minimized while working at different carrier frequencies.