Title :
Reducing energy requirements for instruction issue and dispatch in superscalar microprocessors
Author_Institution :
Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA
Abstract :
Recent studies [MGK 98, Tiw 98] have confirmed that a significant amount of energy is dissipated in the process of instruction dispatching and issue in modern superscalar microprocessors. We propose a model for the energy dissipated by instruction dispatching and issuing logic in modern superscalar microprocessors and validate them through register level simulations and SPICE-measured dissipation coefficients from 0.5 micron CMOS layouts of relevant circuits. Alternative organizations are studied for instruction window buffers that result in energy savings of about 47% over traditional designs.
Keywords :
CMOS digital integrated circuits; SPICE; circuit simulation; instruction sets; low-power electronics; microprocessor chips; 0.5 micron; CMOS; SPICE-measured dissipation coefficients; energy requirements; instruction dispatch; instruction issue; instruction window buffers; register level simulations; superscalar microprocessors; CMOS logic circuits; Circuit simulation; Computer science; Decoding; Dispatching; Microprocessors; Minimization; Modems; Permission; Semiconductor device modeling;
Conference_Titel :
Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on
Print_ISBN :
1-58113-190-9
DOI :
10.1109/LPE.2000.155287
