A novel single electron SRAM architecture

Author

Mahapatra, Santanu ; Ionescu, Adrian Mihai

Author_Institution

Electron. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland

fYear

2004

fDate

16-19 Aug. 2004

Firstpage

287

Lastpage

289

Abstract

A novel single electron transistor (SET) based architecture is proposed for SRAM application. The proposed architecture is composed of two cross-connected SETs and exhibits negative differential resistance (NDR) characteristics, which is exploited to obtain unique tunable hysteresis effects and Schmitt trigger like operation. As no capacitor is used for information storage and SETs offer nano scale feature size, proposed architecture promises to be attractive candidate for highly dense SRAM structure.

Keywords

SRAM chips; integrated circuit design; integrated circuit modelling; memory architecture; negative resistance; negative resistance circuits; negative resistance devices; semiconductor device models; single electron transistors; trigger circuits; SRAM application; Schmitt trigger; negative differential resistance; single electron SRAM architecture; single electron transistor based architecture; tunable hysteresis effects; Analytical models; Capacitance; Hysteresis; Power dissipation; Random access memory; Single electron memory; Single electron transistors; Temperature; Tunable circuits and devices; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Nanotechnology, 2004. 4th IEEE Conference on

Print_ISBN

0-7803-8536-5

Type

conf

DOI

10.1109/NANO.2004.1392327

Filename

1392327