Title :
Silicon nanocrystals: from Coulomb blockade to memory arrays
Author :
Steimle, R.F. ; Rao, R. ; Sadd, M. ; Swift, C. ; Hradsky, B. ; Straub, S. ; Merchant, T. ; Stoker, M. ; Parikh, C. ; Anderson, S. ; Rossow, M. ; Yater, J. ; Acred, B. ; Harber, K. ; Prinz, E. ; White, B.E., Jr. ; Muralidhar, R.
Author_Institution :
Technol. Solutions Organ., Motorola SPS, Austin, TX, USA
Abstract :
Silicon nanocrystals provide opportunity to solve the challenging problem of tunnel oxide scaling of conventional flash memories by increasing immunity to charge loss via tunnel oxide defects. New aspects in silicon nanocrystal memory technology include Coulomb blockade or charge confinement effects, atomistic nucleation, and nanocrystal passivation to preserve them during subsequent processing and program/erase endurance characteristics. This paper discusses the above characteristics and culminates in presenting salient results from 4 Mb NOR memory arrays fabricated using 90 nm CMOS technology. Excellent memory characteristics including tight Vt distributions are obtained using a tunnel oxide thickness of 5 nm and a 6 V power supply.
Keywords :
CMOS memory circuits; Coulomb blockade; NOR circuits; elemental semiconductors; flash memories; nanoelectronics; nanostructured materials; passivation; programmable logic arrays; silicon; 4 Mbit; 5 nm; 6 V; 90 nm; CMOS technology; Coulomb blockade; NOR memory arrays; Si; atomistic nucleation; charge confinement effects; charge loss; flash memories; memory arrays; nanocrystal passivation; program-erase endurance properties; silicon nanocrystal memory technology; silicon nanocrystals; tunnel oxide defects; tunnel oxide scaling; tunnel oxide thickness; CMOS technology; Capacitance; Electrons; Energy states; Fabrication; Nanocrystals; Nonvolatile memory; Pressure control; Silicon; Threshold voltage;
Conference_Titel :
Nanotechnology, 2004. 4th IEEE Conference on
Print_ISBN :
0-7803-8536-5
DOI :
10.1109/NANO.2004.1392328