Implementation of Multi-Rate Quasi-Cyclic Low-Density Parity-Check Codes

This paper investigates the implementation of multi-rate low-density parity-check (QC-LDPC) codes. We propose a novel scheme to construct multi-rate QC-LDPC codes from the regular mother codes. These QC-LDPC codes can share a single particular decoder which is designed for the regular QC-LDPC code previously in spite of either irregularity or regularity. Based on this construction, encoding of the multi-rate QC-LDPC codes also can be implemented by a single particular encoder with simple shift registers at encoding speeds linearly proportional to the number of parity-check bits of a code for parallel encoding and to the length of information sequence of a code for serial encoding. The QC-LDPC codes at various rates possess different encoding speeds in a given hardware complexity which is determined by the mother code for parallel encoding and by the lowest-rate code for serial encoding.