DocumentCode
2534157
Title
[Title page i]
fYear
2010
fDate
3-6 May 2010
Abstract
The paper deals with the following topics:formal logic; physical synthesis; low-power circuits; harvesting; synchronisers; high level synthesis; retiming; power-performance optimisation; arbitration; delay insensitivity; and GasP.
Keywords
asynchronous circuits; electronic engineering computing; formal logic; formal verification; high level synthesis; low-power electronics; optimisation; synchronisation; GasP; arbitration; delay insensitivity; formal logic; harvesting; high level synthesis; low-power circuits; physical synthesis; power-performance optimisation; retiming; synchronisers;
fLanguage
English
Publisher
ieee
Conference_Titel
Asynchronous Circuits and Systems (ASYNC), 2010 IEEE Symposium on
Conference_Location
Grenoble
ISSN
1522-8681
Print_ISBN
978-0-7695-4032-0
Type
conf
DOI
10.1109/ASYNC.2010.1
Filename
5477018
Link To Document