A Taylor Expansion Diagram Approach for Nano-CMOS RTL Leakage Optimization

Due to exponential behavior of gate-oxide leakage current with temperature and technology scaling, leakage power plays important role in nano - CMOS circuit. In this paper, we present simultaneous scheduling and binding algorithm for optimizing leakage current during behavioral synthesis. It uses TED (Taylor Expansion Diagram) for generating optimized DFG (Data Flow Graph). Once DFG is obtained, it selectively binds non-critical components to corresponding functional unit consisting of transistors of high oxide thickness and critical components with low oxide thickness. As the algorithm considers time-constraint explicitly, it reduces leakage current without degrading the performance of the design. Experimental results on a set of behavioral synthesis benchmarks for 45 nm process show 30% to 70% reduction in leakage current compared to the results obtained by a conventional optimization flow.