Memory-Based Computation of Inner-Product for Digital Signal Processing Applications

In this paper, we present the optimization schemes for the implementation of inner-products using distributed arithmetic (DA) and look-up-table (LUT)-based multipliers. The optimized designs of both these approaches need the same number of LUTs and the same number of adders to produce the same throughput rate. But, the DA-based design needs adders of less width, while the LUT-multiplier based design requires less number of LUT words. The optimized designs for different inner-product lengths are synthesized by Synopsys Design Compiler using 90 nm CMOS library for input word-length L=8 and 16 for coefficient word-length W=8. Both the approaches are found to have nearly the same time-complexity, but the LUT-multiplier based design has significantly lower area-complexity, so as to offer a saving of more than 30% of area-delay product, in average, over the other.