Test of Embedded Content Addressable Memories

Delay faults in content addressable memories (CAMs) is a major concern in many applications such as network routers, IP filters, longest prefix matching (LPM) search engines and cache tags where high speed data search is significant. It creates the need for analysis of critical paths and detecting associated faults using minimum number of test patterns. This paper proposes a test method to detect different faults of CAM systems using a newly proposed enhanced power-performance (EPP) cell structure. The proposed CAM faults test (CFT) algorithm is using minimum number of operations such as 5m+2n+4. It covers pseudo CMOS logic faults and cell coupling faults of both search and storage circuitries of CAM cells with improved fault coverage.