A Variation Aware Circuit Design Using Dynamic Clock Stretching

In the nanometer era, process, voltage and temperature variations are dominating circuit performance, power and yield. Over the past few years, statistical optimization methods have been effective in improving yield in the presence of uncertainty due to process variations. However, statistical methods over consume resources, even in the absence of variations. Hence, to facilitate a better performance-power-yield tradeoff, techniques that can dynamically enable variation compensation are becoming necessary. In this paper, we propose a dynamic technique that controls the instance of data capture in critical path flops, by delaying the clock edge trigger. The methodology employs a dynamic delay detection circuit to identify the uncertainty in delay due to variations and stretches the clock in the destination flip-flops. The delay detection circuit uses a latch and set of combinational gates to dynamically detect and create the slack needed to accommodate the delay due to variations. The clock stretching logic (CSL) is only added to paths, which has a high probability of failure in the presence of variations. The proposed methodology improves the timing yield of the circuit without significant over compensation. Experimental results based on Monte-Carlo simulations on benchmark circuits indicate efficient improvement in timing yield with a small area overhead.