Regular array of nanometer-scale devices performing logic operations with fault-tolerance capability

This paper addresses the functional robustness and fault-tolerance capability of very-deep submicron CMOS and single-electron transistor (SET) circuits. A four-layer circuit architecture is proposed, and a set of guidelines is identified for the design of very high-density digital systems using inherently unreliable and error-prone devices. The proposed architecture is based on the principle of graceful degradation of circuit performance allowing recovery of information, where classical circuits would fail. The integration of the proposed architecture is shown as a regular and compact PLA-style design, allowing the adaptability of the redundancy factor.