Test Wrapper Design for 3D System-on-Chip Using Optimized Number of TSVs

Manufacturing of 3D stacked IC chips has became feasible recently. But testing of these 3D ICs is becoming important in the semiconductor industry. Now a days also embedded core based 3D ICs are equally popular. Hence the increased complexity in the chips becomes a constraint for the test engineers. This paper addresses a 1500-style wrapper optimization in 3D ICs based on Through Silicon Vias(TSVs) for vertical interconnects. This work minimizes scan test time with the optimum number of TSVs available for testing. The results are presented based on the ITC´02 SOC test benchmarks. The simulation results show that small number of TSVs are sufficient to test the embedded cores in the SOC.