• DocumentCode
    2534737
  • Title

    Easily testable realization based on OR-AND-EXOR expansion with single rail inputs

  • Author

    Hirayama, Takashi ; Koda, Goro ; Nishitani, Yasuaki ; Shimizu, Kensuke

  • Author_Institution
    Dept. of Comput. Sci., Gunma Univ., Japan
  • fYear
    1998
  • fDate
    24-27 Nov 1998
  • Firstpage
    371
  • Lastpage
    374
  • Abstract
    It is known that AND-EXOR two-level networks obtained by AND-EXOR expansion with positive literals are easily testable. They are based on the single-rail-input logic, and require (n+4) tests to detect their single stuck-at faults, where n is the number of the input variables. We present three-level networks obtained from the single-rail-input OR-AND-EXOR expansion and propose a more easily testable realization than the AND-EXOR networks. The realization is an OR-AND-EXOR network which limits the fan-in of the AND and OR gates to n/r and r respectively, where r is a constant (1⩽r⩽n). We show that only (r+n/r) tests are required to detect all the single stuck-at faults by adding r extra variables to the network
  • Keywords
    design for testability; fault diagnosis; integrated circuit testing; integrated logic circuits; logic design; logic testing; DFT; OR-AND-EXOR expansion; OR-AND-EXOR networks; single stuck-at faults; single-rail-input logic; testable realization; three-level networks; Circuit faults; Circuit testing; Computer science; Electrical fault detection; Electronic mail; Equations; Fault detection; Input variables; Logic testing; Rails;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on
  • Conference_Location
    Chiangmai
  • Print_ISBN
    0-7803-5146-0
  • Type

    conf

  • DOI
    10.1109/APCCAS.1998.743779
  • Filename
    743779