Interconnect and Device Scaling Trends in CMOS VLSI

Abstract form only given. This talk is an introductory survey of on-chip interconnect scaling trends in VLSI systems. Fundamental concepts related to on-chip interconnection with an emphasis on circuit design impact and process architecture are discussed. An overview of key evolving trends as reflected in the International Semiconductor Technology Roadmap for interconnect is presented. Some simple metrics that address system wireability and performance are introduced and an overview of challenges that need to be met to define optimal interconnect architectures is then reviewed. The presentation will provide insight into how interconnect architecture is designed and what some of the key tradeoff´s encountered are. Emerging trends such as 3D stacking, scattering mechanisms in wires and other challenges to continued scaling of interconnect are also reviewed. To better understand the relationship between wires and devices and their scaling trends, a brief review of basic CMOS transistor physics, device scaling trends and implications for design and performance is also covered. As scaling limitations for traditional CMOS devices is approached other emerging transistor architectures are also briefly discussed.