A PLC program generator incorporating sequential circuit synthesis techniques

Programmable Logic Controllers (PLC) are normally programmed by using ladder diagrams which represent the interconnection of the “virtual devices” needed to perform the desired functions. While this method is convenient and easy to implement in most cases, it can become quite complicated when timers and counters are included. This problem is overcome by incorporating the techniques of sequential circuit synthesis into the PLC program generator. The program generator accepts inputs in the form of State Transition Description Language (STDL) statements and its final output is in the form of the target PLC machine code. A built-in minimization capability makes the output code run more efficiently