DSP memory allocation method for indirect addressing with wide range update operation by multiple registers

A novel method to derive an efficient memory access pattern for digital signal processors (DSPs), of which memory is accessed only by address registers (ARs), is proposed. In this paper, the AR update scheme is extended such that address can be efficiently modified within ±k in addition to conventional ±1 updates. The method formulates program variables and AR modifications by a graph, and extracts a maximum chained clique graph with k+1 vertices, which is accessed only by AR update operations within ±k, so that the estimated number of overhead codes is minimized. In order to utilize multiple ARs, a method to assign memory accesses into ARs is also studied. The proposed methods are applied to a DSP compiler, and memory allocations derived for several examples are compared with memory allocations by other methods